It is known in the LSI technology to place flip-flops in a logic circuit so that they are triggered into a set condition in response to an error bit that occurs in the logic circuit during normal circuit operations. During a test mode, the flip-flops are brought into a series circuit, or scan path, and a read pulse is applied along the scan path to read out the contents of the flip-flops into a diagnostic circuit to determine the location of the error. Scan path connection is determined at the stage of logic circuit design in order to allow computer simulations to be performed on the whole circuitry including the scan path. No alterations are made on the flip-flops during a later stage of design in which the placement and wiring of logic elements are determined. The placement or logic elements, on the other hand, is made according to a connecting algorithm so that individual logic elements to be connected are not spaced far apart from each other. In addition to the scan-path connection, a number of other connections are necessary for the scan-path flip-flops. Because of the geometric design requirements of a particular logic circuit, the sequence in which the flip-flops are arranged is not necessarily optimum for the wiring pattern of the logic elements. Under such circumstances, some logic elements located far apart from each other must be wired together. However, it involves a long meandering path which reduces the amount of channel space dedicated for other circuit connections.